In memory devices and other integrated circuits, it is often desired or necessary to initialize or reset the circuitry, which may include setting internal latches to a definite state. The input pins may be configured by the end user to be in a logic state “1” (electrically connected to a voltage Vcc), to be in a logic state “0” (electrically connected to a ground potential), or to be left floating. In the case in which the input is configured in a logic state “1”, then a circuit is used to make sure that the input is automatically tied to Vcc during the power on reset function of the device. In the cases where the input is configured in a logic state “0” or is floating, then a circuit is used to make sure that the input is automatically tied to ground during the power on reset function of the device.
In the prior art, circuits having internal paths from the input line through a resistor to another Vcc or ground have been effective for setting the internal latches to the correct state. However, a problem can occur in some conditions using these circuits in that a current can flow back to the input pin. This problem occurs when the input pin is to be tied to ground but the internal path is coupled to Vcc and also when the input pin is tied to Vcc but the internal path is coupled to ground. Thus there is a current flowing, and power is consumed, even when the device is not in operation. This power consumption is a problem, especially when the integrated circuit is installed in an end product such as a cellular phone that has batteries, in that the battery life is shortened.
One solution in the prior art to correct this problem has been to employ a latch circuit, as for example that shown in FIG. 2, which effectively eliminates the standby current. However, it has been found that typical latch circuits for automatically connected the input pin to the desired state (“0” or “1” or “floating”) do not operate correctly for every possible situation. For example, the graphs in FIGS. 3a–3c, show the case in which the latch in FIG. 2 has its input pins 31 is tied to Vcc through a capacitor (which is generally the case when the input pin is floating). In this case it is desired that the autoground function of transistor 33 be operational during and after power-on reset. For this to occur, the output 37 of the NAND gate 35 at node Y must be a logic “1”, in order to turn on NMOS transistor 33 and pull the input line 32 at node X down to a ground potential. The input line 32 is one input to the NAND gate 35 while the other input is the power on reset signal (PORL) which is an active low signal. Referring to the graphs in FIGS. 3a–3c: During stage 1 of operation input Vcc 40 is increasing, the power on reset PORL signal (curve 42) is ramping up to a logic “1”. The voltage (curve 50) at Node Y is at logic “0”, and the voltage (curve 60) at node X is tracking the Vcc. When the PORL signal is applied (stage 2 of the graphs), then the PORL signal goes low, and Vcc 40 continues to increase. The effect on Nodes X and Y will be dependent on whether the pull-down transistor 33 is strong enough to pull down the voltage on the input line 32 to a voltage corresponding to the logic level “0” for the NAND gate 35. When the transistor 33 is a strong pull-down transistor, then in stage 2 of the graphs, the node X goes according to curve 61 pulling down to a logic “0” voltage level. According to the truth table for a NAND gate, in stage 2, the power on reset PORL signal is low, which guarantees that the output of the NAND gate (node Y) will be “1”, regardless of the voltage at node X. However, in stage 3, when the PORL signal turns off (goes high) then the voltage at node Y will be dependent on the voltage at node X. In the case of a strong pull-down transistor 33, node X will be pulled down to “0” (curve 61), resulting in node Y going to “1” (curve 51). This is a desired result, as the autoground circuit will work properly. However, if the transistor 33 is a weak pull down, then the Vcc will pull node X up to a high (“1”) value (curve 62), which results in the node Y becoming a “0” (curve 52). This is not desired, as this just latches in a “0” and the transistor 33 turns off, keeping node X at a high voltage logic level, and preventing the autoground circuit from functioning.
In another example, the graph in FIGS. 4a–4c show the case in which the latch in FIG. 2 has its input pin tied to Vcc through a resistor (which is generally the case when the input pin is tied to Vcc). In this case, it is desired that the autoground function through transistor 33 not be operational during and after power-on reset. (In this case, we want an “autoVCC” instead). For this to occur, the output 37 of the NAND gate 35 at node Y must be a logic “0”, in order to turn off NMOS transistor 33 so that the input line at node X is pulled up to a high voltage potential (Vcc). One input 33 to the NAND gate 35 is the voltage value at node X, while the other input is the power on reset signal (PORL) which is an active low signal. Referring to the graphs in FIGS. 4a–4c: During stage 1 of the operation (before the PORL signal), input Vcc 40 is increasing, the power on reset signal 42 is ramping up to a logic “1”. The voltage at Node Y 50 is at logic “0”, and the voltage at node “X” 80 is tracking the Vcc. When the PORL signal 42 is applied (stage 2 of the graphs), then the PORL signal goes low, and Vcc 40 continues to increase. The effect on Nodes X and Y will be dependent on whether the pull-down transistor 33 is strong enough to pull down the voltage on the input line to a voltage corresponding to the logic level “0” for the NAND gate. When the transistor 33 is a strong pull-down transistor, then in stage 2 of the graphs, the node X goes according to curve 81 pulling down to a logic “0” voltage level. According to the truth table for a NAND gate, in stage 2, the power on reset signal is low, which guarantees that the output of the NAND gate (node Y) will be “1”, regardless of the voltage at node X. However in stage 3, when the PORL signal turns off (goes high) then the voltage at node Y will be dependent on the voltage at node X. In the case of a strong pull-down transistor 33, node X will be pulled down to “0” (curve 81), resulting in node Y going to “1” (curve 71). This is not the desired result, as the Vcc circuit will not work properly, as the transistor 33 is pulling the input line 32, down to a ground potential. Thus, in the case when the transistor is a strong pull down, the auto Vcc circuit does not operate properly.
In U.S. Patent Application Publication U.S. 2003/0214337A1, Miyagi attempts to the avoid the problem of reliable resetting of latches during power-on, by providing an RS latch with a depletion-type MIS transistor to ensure that it always starts in a specified state.
Another way to solve this problem is to require end-user customers to ground otherwise unconnected input pins. But since it is normally desired to give customers flexibility as to how to connect (or not connect) the input pins, requiring the customer to ground all unused input pins is not a desired solution to this problem.
In U.S. Pat. No. 6,335,648, Matsushita describes one attempt at enhancing the stability of integrated circuits in a reset condition. It uses an RS flip-flop that is actively set by a reset signal, and whose output is applied to an n-channel pull-down transistor coupled through a resistor between an output NODE and ground. Additional circuitry, including an OR gate coupled to inverting buffers, is used for resetting the flip-flop so that it does not interfere with normal operation after the reset condition has concluded. However, a simpler circuit is desired.
It is desired to have input pins be tied automatically to a definite voltage potential during a reset condition, in order to avoid the problems noted above, without taking away customer flexibility as to how to use the input pins in normal operation. It is desired that such an auto-clamping circuit be relatively simple in construction, work in every situation (input pin grounded, tied to the Vcc power supply or left floating) without relying on the strength of a latch's pull-down transistor, and not draw unnecessary current and power.